1. Field of the Invention
The present invention relates to an output timer for use in household electrical appliances such as microprocessor-controlled rice boilers, products such as motor vehicles, and manufactured goods.
2. Description of the Prior Art
Referring now to FIG. 9, there is illustrated a block diagram showing the structure of an example of a prior art output timer. In the figure, reference numeral 1 denotes an event terminal to which an event signal for indicating the occurrence of an event is applied, reference numeral 2 denotes a free running up-counter which is built to continue to run unless a stop signal from outside is applied thereto even though an event signal is applied to the output timer, and which counts clock pulses applied thereto at predetermined intervals, and increments and holds the count as a numerical count value, and reference numeral 3 denotes a compare register into which a predetermined value to be compared with the count value held by the free running up-counter 2 can be written via a data bus 16 by a CPU 15. Reference numeral 4 denotes a comparator for comparing the count value held by the free running up-counter 2 with the predetermined value written into the compare register 3, and for furnishing a coincidence signal when they are coincident, that is, when they are equal to each other, and reference numeral 5 denotes a set-reset flip-flop having its set terminal S connected to the event terminal 1, its reset terminal R connected to the output terminal of the comparator 4, and its output terminal OUT.
Referring next to FIG. 10, there is illustrated a timing chart showing the operation of the prior art output timer shown in FIG. 9. A description will be made as to the operation of the prior art output timer with reference to FIGS. 9 and 10.
When an event occurs, an event signal informing the occurrence of the event is applied to the event terminal 1 if it is necessary to activate the output timer. The event signal applied to the event terminal 1 is then delivered to the set terminal S of the set-reset flip-flop 5. As a result, an output signal which appears at the output terminal OUT of the set-reset flip-flop 5 makes a LOW to HIGH transition. Simultaneously, the event signal applied to the event terminal 1 is also delivered, as an interrupt signal, to the CPU 15. In response to the interrupt signal, the CPU 15 reads the count value (a) held by the free running up-counter 2 by way of the data bus 16. The CPU 15 then adds a preprogrammed value (x) to be added, which is equal to an increment corresponding to the duration of a one-shot pulse asserted HIGH of the output signal which will appear at the output terminal OUT, to the read count value (a) of the free running up-counter 2, and stores the addition result (a+x) in the compare register 3 by way of the data bus 16.
After that, the comparator 4 starts to compare the current count value held by the free running up-counter 2 with the addition result (a+x) stored in the compare register 3. When they are equal to each other, the comparator 4 furnishes a coincidence signal indicating that they are equal to each other to the reset terminal R of the set-reset flip-flop 5. As a result, the set-reset flip-flop 5 is reset and hence the output signal which appears at the output terminal OUT is caused to make a HIGH to LOW transition. The output timer thus completes the delivery of a one-shot output pulse asserted HIGH having the duration which corresponds to the predetermined value (x) to be added.
Similarly, when another event occurs and the CPU 15 then reads the current count value (b) of the free running up-counter 2, the CPU 15 adds the preprogrammed value (x) to be added to the read count value (b) of the free running up-counter 2, and stores the addition result (b+x) in the compare register 3 by way of the data bus 16. The comparator 4 then starts to compare the current count value held by the free running up-counter 2 with the addition result (b+x) stored in the compare register 3. When they are equal to each other, the comparator 4 furnishes a coincidence signal indicating that they are equal to each other to the reset terminal R of the set-reset flip-flop 5. As a result, the set-reset flip-flop 5 is reset and hence the output signal which appears at the output terminal OUT is caused to make a HIGH to LOW transition. The output timer thus completes the delivery of a further one-shot output pulse asserted HIGH having the duration which corresponds to the predetermined value (x) to be added, like the aforementioned case.
The prior art output timer which is constructed as mentioned above needs to furnish an interrupt request to the CPU 15 so as to cause the CPU 15 to handle the interrupt, that is, read the count value held by the free running up-counter 2, add a predetermined value (x) to be added to the count value, and store the addition result in the compare register 3, each time an event occurs. Thus, a problem with the prior art output timer is that the load on the CPU 15 is increased.
Furthermore, since a measure of time is needed in order for the CPU 15 to handle the interrupt, there is a possibility that the count value held by the free running up-counter 2 exceeds the addition result before the addition result is stored in the compare register 3 and hence the set-reset flip-flop 5 is kept in a state wherein it is not reset. In such a case, the output timer cannot provide desired output pulses.